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W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 1 - features 3.3v 0.3v power supply comply to pc133/100/66 specification 2,097,152 words x 4 banks x 8 bits organization auto refresh and self refresh cas latency: 2 and 3 burst length: 1, 2, 4, 8 , and full page sequential and interleave burst burst read, single writes mode byte data controlled by dqm power-down mode auto-precharge and controlled precharge 4k refresh cycles / 64ms interface: lvttl package: tsop ii 54 pin, 400 mil - 0.80 general description W986408BH is a high speed synchronous dynamic random access memory (sdram ) , organized as 2m words x 4 banks x 8 bits. using pipelined architecture and 0.25um process technology, W986408BH delivers a data bandwidth of up to 133m (- 75) bytes per second. to fully comply to the pc133/100/66 personal computer industrial standard, W986408BH is sorted into four speed grades: -75, -8h, -8n, and -10. the ?75 is compliant to the pc133/cl3 specification, -8h is compliant to the pc100/cl2 specification, the -8n is compliant to pc100/cl3 specification, and -10 is compliant to pc/66 specification. accesses to the sdram are burst oriented. consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically generated by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving among internal banks to hide the precharging time. by having a programmable mode register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986408BH is ideal for main memory in high performance applications. key parameters symbol description min/max -75 -8h -8n -10 t ck clock cycle time min 7.5ns 8ns 10ns 10ns t ac access time from clk max 5.4ns 6ns 6ns 8ns t rp precharge to active command min 20ns 20ns 20ns 30ns t rcd active to read/write command min 20ns 20ns 20ns 30ns i cc1 operation current ( single bank ) max 90ma 90ma 90ma 70ma i cc4 burst operation current max 140ma 140ma 140ma 110ma i cc6 self-refresh current max 1ma 1ma 1ma 1ma
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 2 - dq0 dq7 dqm clk cke cs ras cas we a10 a0 a9 a11 bs0 bs1 . clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer block diagram column decoder sense amplifier cell array bank #1 note: the cell array configuration is 4096 * 512 *8. dmn row decoder row decoder row decoder row decoder
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 3 - pin assignment pin number pin name function description 23 ~ 26, 22, 29 ~35 a0~ a11 address multiplexed pins for row and column address. row address : a0 ~ a11. column address: a0 ~ a8. 20, 21 bs0, bs1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. 2, 5, 8, 11, 44, 47, 50, 53 dq0 ~ dq7 data input/ output multiplexed pins for data output and input. 19 cs# chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. 18 ras# row address strobe command input. when sampled at the rising edge of the clock, ras#, cas# and we# define the operation to be executed. 17 cas# column address strobe referred to ras# 16 we# write enable referred to ras# 39 dqm input/output mask the output buffer is placed at hi- z(with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. 38 clk clock inputs system clock used to sample inputs on the rising edge of clock. 37 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. 1, 14, 27 v cc power ( +3.3 v ) power for input buffers and logic circuit inside dram. 28, 41, 54 v ss ground ground for input buffers and logic circuit inside dram. 3, 9, 43, 49 v cc q power ( + 3.3 v ) for i/o buffer separated power from v cc , used for output buffers to improve noise. 6, 12, 46, 52 v ss q ground for i/o buffer separated ground from v ss , used for output buffers to improve noise. 4, 7, 10, 13, 15, 36, 40, 42, 45, 48, 51 nc no connection no connection
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 4 - pin assignment (top view) v ss dq7 v ss q nc dq6 v cc q nc dq5 v ss q nc dq4 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc dq0 v cc q nc dq1 v ss q nc dq2 v cc q nc dq3 v ss q nc v cc nc we cas ras cs bs0 bs1 a10/ap a0 a1 a2 a3 v cc
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 5 - absolute maximum ratings symbol item rating unit notes v in ,v out input, column output voltage -0.3~v cc +0.3 v 1 v cc ,v cc q power supply voltage -0.3~4.6 v 1 t opr operating temperature 0~70 c 1 t stg storage temperature -55~150 c 1 t solder soldering temperature(10s) 260 c 1 p d power dissipation 1 w 1 i out short circuit output current 50 ma 1 recommended dc operating conditions ( ta = 0 to 70 c ) symbol parameter min typ max unit notes v cc power supply voltage 3.0 3.3 3.6 v 2 v cc q power supply voltage (for i/o buffer) 3.0 3.3 3.6 v 2 v ih input high voltage 2.0 - v cc +0.3 v 2 v il input low voltage -0.3 - 0.8 v 2 note: v ih (max) = v cc /v cc q+1.2v for pulse width < 5ns v il (min) = v ss /v ss q-1.2v for pulse width < 5ns capacitance (v cc =3.3v, af = 1mhz, ta=25 c) symbol parameter min max unit input capacitance (a0 to a11, bs0 ,bs1, cs, ras, cas, we, dqm, cke) - 4 pf c i input capacitance (clk) - 4 pf c o input/output capacitance - 6.5 pf note: these parameters are periodically sampled and not 100% tested.
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 6 - ac characteristics and operating condition (vcc=3.3v 0.3v, ta=0 to 70 c notes:5, 6, 7, 8) -75 -8h -8n -10 symbo parameter min max min max min max min max unit t rc ref/active to ref/active command 65 68 72 90 t ras active to precharge command period 45 100000 48 100000 48 100000 60 100000 ns t rcd active to read/write command delay 20 20 20 30 t ccd read/write(a) to read/write(b)command 1 1 1 1 cycle t rp precharge to active command period 20 20 20 30 t rrd active(a) to active(b) command period 15 20 20 20 t wr write recovery time cl*=2 10 10 12 15 cl*=3 7.5 8 10 10 t ck clk cycle time cl*=2 10 1000 10 1000 12 1000 15 1000 cl*=3 7.5 1000 8 1000 10 1000 10 1000 t ch clk high level width 2.5 3 3 3 t cl clk low level width 2.5 3 3 3 t ac access time from clk cl*=2 6 6 7 9 cl*=3 5.4 6 6 8 ns t oh output data hold time 2.7 3 3 3 t hz output data high impedance time 2.7 7.5 3 8 3 8 3 10 t lz output data low impedance time 0 0 0 0 t s b power down mode entry time 0 7.5 0 8 0 8 0 10 t t transition time of clk (rise and fall) 0.5 10 0.5 10 0.5 10 0.5 10 t ds data-in set-up time 1.5 2 2 3 t dh data-in hold time 0.8 1 1 1 t as address set-up time 1.5 2 2 3 t ah address hold time 0.8 1 1 1 t cks cke set-up time 1.5 2 2 3 t ckh cke hold time 0.8 1 1 1 t cms command set-up time 1.5 2 2 3 t cmh command hold time 0.8 1 1 1 t ref refresh time 64 64 64 64 ms t rsc mode register set cycle time 15 16 16 20 ns * cl=cas latency
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 7 - dc characteristics (v cc = 3.3v 0.3v, ta=0 ~70 c) -75/-8h/-8n -10 items symbol min. max. min. max. unit notes operating current t ck= min , t rc =min i cc1 90 70 3 active precharge command cycling without burst operation 1 bank operation standby current t ck =min , cs#=v ih cke = v ih i cc2 50 40 3 v ih/l =v ih(min) /v il(max) bank : inactive state cke = v il (power down mode) i cc2p 1 1 3 standby current clk=v il , cs#=v ih cke = v ih i cc2s 8 8 v ih/l =v ih (min)/v il (max) bank : inactive state cke = v il (power down mode) i cc2ps 1 1 ma no operating current t ck =min cs#=v ih (min) bank : active state (4 banks) cke = v ih i cc3 65 50 3 burst operating current t ck = min read / write command cycling i cc4 140 110 3,4 auto refresh current t ck = min auto refresh command cycling i cc5 140 110 3 self refresh current(-8h/-8n/-10) self refresh mode cke = 0.2v i cc6 1 1 item symbol min. max. unit notes input leakage current ( 0v v in v cc , all other pins not under test = 0v ) i i(l) -5 5 a output leakage current ( output disable , 0v v out v ccq ) i o(l) -5 5 a lvttl output h level voltage ( i out = -2ma ) v oh 2.4 - v lvttl output l level voltage ( i out = 2ma ) v ol - 0.4 v
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 8 - notes: 1. operation exceeds "absolute maximum rating" may cause permanent damage to the devices. 2. all voltages are referenced to v ss 3. these parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t ck and t rc . 4. these parameters depend on the output loading conditions. specified values are obtained with output open. 5. power up sequence is further described in the "functional description" section. 6. ac testing conditions output reference level 1.4v/1.4v output load see diagram b below input signal levels 2.4v/0.4v transition time (rise and fall) of input signal 2ns input reference level 1.4v output 50pf 7. transition times are measured between v ih and v il . 8. t hz defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 1.2k 0.87k ac test load (a) 1.4 v output z=50 ohms 3.3 v ac test load (b) 50 ohms 50pf
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 9 - operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk. table 1 shows the truth table for the operation commands. table 1 truth table ( note (1) , (2) ) command device state cken-1 cken dqm bs0,1 a10 a11, a9-0 cs ra cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with autoprecharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with autoprecharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no - operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto - refresh idle h h x x x x l l l h self - refresh entry idle h l x x x x l l l h self refresh exit idle (s.r.) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry active h l x x x x x x x x power down mode entry idle active (5) h h l l x x x x x x x x h l x h x h x x clock suspend mode exit active l h x x x x x x x x power down mode exit any (power down) l l h h x x x x x x x x h l x h x h x x data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x notes: (1) v= valid x = don't care l= low level h= high level (2) cken signal is input level when commands are provided. (3) these are state of bank designated by bs0, bs1 signals. (4) device state is full page burst operation. (5) power down mode can not be entered in the burst cycle. when this command asserts in the burst cycle, device state is clock suspend mode.
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 10 - functional description power up and initialization the default power up state of the mode register is unspecified. the following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. during power up, all v dd and v dd q pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "nop" state. the power up voltage must not exceed v dd +0.3v on any of the input pins or v dd supplies. after power up, an initial pause of 200us is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. an additional eight auto refresh cycles (cbr) are also required before or after programming the mode register to ensure proper subsequent operation. programming mode register after initial power up, the mode register set command must be issued for proper device operation. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. the mode register set command is activated by the low signals of ras, cas, cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to trsc has elapsed. please refer to the next page for mode register set cycle and operation table. bank activate command the bank activate command must be applied before any read or write operation can be executed. the operation is similar to ras# activate in edo dram. the delay from when the bank activate command is applied to when the first read or write operation can begin must not be less than the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max). read and write access modes after a bank has been activated , a read or write cycle can be followed. this is accomplished by setting ras high and cas low at the clock rising edge after minimum of t rcd delay. we pin voltage level defines whether the access cycle is a read operation (we high), or a write operation (we low). the address inputs determine the starting column address. reading or writing to a different row within an activated bank requires the bank be precharged and a new bank activate command be issued. when more than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle.
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 11 - burst read command the burst read command is initiated by applying logic low level to cs and cas while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the mode register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the mode register set up cycle. table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. burst write command the burst write command is initiated by applying logic low level to cs, cas and we while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. read interrupted by a read a burst read may be interrupted by another read command. when the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command the is satisfied. read interrupted by a write to interrupt a burst read with a write command, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri-stated. after that point the write command will have control of the dq bus and dqm masking is no longer needed. write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. write interrupted by a read a read command will interrupt a burst write operation on the same clock cycle that the read command is activated. the dqs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. when the read command is activated, any residual data from the burst write cycle will be ignored. burst stop command a burst stop command may be used to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank, if the burst length is full page. use of the burst stop command during other burst length operations is illegal. the burst stop command is defined by having ras and cas high with cs and we low at the rising edge of the clock. the data dqs go to a high impedance state after a delay which is equal to the cas latency in a burst read cycle interrupted by burst stop. if a burst stop command is issued during a full page burst write operation , then any residual data from the burst write cycle will be ignored.
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 12 - table 2 address sequence of sequential mode data access address burst length data 0 n bl= 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl= 4 (disturb addresses are a0 and a1) data 3 n + 3 no address carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl= 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 . addressing sequence of sequential mode a column access is performed by increasing the address from the column address which is input to the device. the disturb address is varied by the burst length as shown in table 2. . addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bit in the sequence shown in table 3. table 3 address sequence of interleave mode data access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 8 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 13 - auto-precharge command if a10 is set to high when the read or write command is issued, then the auto-precharge function is entered. during auto- precharge, a read command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. the number of clocks is determined by cas latency. a read or write command with auto-precharge can not be interrupted before the entire burst operation is completed. therefore, use of a read, write, or precharge command is prohibited during a read or write cycle with auto-precharge. once the precharge operation has started, the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. issue of auto-precharge command is illegal if the burst is set to full page length. if a10 is high when a write command is issued, the write with auto- precharge function is initiated. the sdram automatically enters the precharge operation one clock delay from the last burst write cycle. this delay is referred to as write t dpl . the bank undergoing auto-precharge can not be reactivated until t dpl and t rp are satisfied. this is referred to as t dal , data-in to active delay (t dal = t dpl + t rp ). when using the auto-precharge command, the interval between the bank activate command and the beginning of the internal precharge operation must satisfy t ras (min). precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is entered when cs, ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. three address bits, a10, a12, and a13, are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the precharged bank must be reactivated before a new read or write access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). self refresh command the self refresh command is defined by having cs, ras, cas and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the device will exit self refresh operation after cke is returned high. a minimum delay time is required when the device exits self refresh operation and before the next command can be issued. this delay is equal to the ras cycle time plus the self refresh exit time. power down mode the power down mode is initiated by holding cke low. all of the receiver circuits except cke are gated off to reduce the power. the power down mode does not perform any refresh operations, therefore the device can not remain in power down mode longer than the refresh period (t ref ) of the device. the power down mode is exited by bringing cke high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t ces (min) + t ck (min). no operation command the no operation command should be used in cases when the sdram is in a idle or a wait state to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras, cas, and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 14 - deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras, cas, and we signals become don't cares. clock suspend mode during normal access mode, cke must be held high enabling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. there is a one clock delay between the registration of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bringing cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited.
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 15 - timing waveform tck clk a0-a11 bs0, 1 v ih v il tcms tcmh tcms tcmh tcms tcmh tcms tcmh tas tah tcmh tcms tch tcl tt tt tcks tckh tckh tcks tcks tckh command input timing cs ras cas we cke
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 16 - read timing read cas latency tac tlz tac toh thz toh burst length read command clk cs ras cas we a0-a11 bs0, 1 dq valid data-out valid data-out
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 17 - tcmh tcms tcmh tcms tds tdh tds tdh tds tdh tds tdh valid data-out valid data-out valid data-out valid data-in valid data-in valid data-in valid data-in tckh tcks tckh tcks tds tdh tds tdh tdh tds tds tdh valid data-in valid data-in valid data-in valid data-in tcmh tcms tcmh tcms toh tac toh tac toh thz open tlz tac toh tac tckh tcks tckh tcks toh tac toh tac toh tac toh tac valid data-out valid data-out valid data-out clk dqm dq0 -7 (word mask) (clock mask) clk cke dq0 -7 clk control timing of input data control timing of output data (output enable) (clock mask) dqm dq0 -7 cke clk dq0 -7
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 18 - mode register set cycle a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 bs0 a0 a11 a0 bs1 "0" "0" a0 a3 a0 addressing mode a0 0 a0 sequential a0 1 a0 interleave a0 a9 single write mode a0 0 a0 burst read and burst write a0 1 a0 burst read and single write a0 a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 burst length a0 sequential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 reserved a0 reserved a0 full page a0 cas latency a0 reserved a0 reserved 2 a0 3 4 a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 trsc tcms tcmh tcms tcmh tcms tcmh tcms tcmh tas tah clk cs ras cas we a0-a10 bs register set data next command a0 reserved "0" "0" "0" "0"
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 19 - operating timing example 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 interleaved bank read (burst length = 4, cas latency = 3) (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 trc trc trc trc tras trp tras trp trp tras tras trcd trcd trcd trcd tac tac tac tac trrd trrd trrd trrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 idle bank #1 bank #2 bank #3
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 20 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 interleaved bank read (burst length = 4, cas latency = 3, autoprecharge) (clk = 100 mhz) clk cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 trc trc trc tras trp tras trp tras trp tras trcd trcd trcd trcd tac tac tac tac trrd trrd trrd trrd active read active read active active active read read trc raa rbb rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 ap* ap* ap* raa caw rbb cbx rac cay rbd rae cbz
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 21 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 trc trc trc tras trp tras trp tras trp trcd trcd trcd trrd trrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 interleaved bank read (burst length=8, cas latency=3) (clk = 100 mhz) clk dq cke dqm a0-a9 a11 a10 bs0 we cas ras cs bs1 active read precharge active read precharge active tac tac read precharge tac bank #0 idle bank #1 bank #2 bank #3
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 22 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 trc trc tras trp tras tras trp trcd trcd trcd trrd trrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby interleaved bank read (burst length=8, cas latency=3, autoprecharge) (clk = 100 mhz) rac rac caz * ap is the internal precharge start timing active read active active read tcac tcac tcac clk dq cke dqm a0-a9 a10 bs1 we cas ras cs bank #0 idle bank #1 bank #2 bank #3 read ap* ap* bs0
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 23 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 trc tras trp tras trp trcd trcd trcd trrd trrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 interleaved bank write (burst length=8) (clk = 100 mhz) write precharge active active write precharge active write clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 idle bank #0 bank #1 bank #2 bank #3 tras
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 24 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 trc tras trp tras tras trp trcd trcd trcd trrd trrd raa raa cax rbb rbb cby rab rac ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz interleaved bank write (burst length=8, autoprecharge) (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active write write active bank #0 idle bank #1 bank #2 bank #3 ap* active write ap*
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 25 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 tccd tccd tccd tras trp tras trp trcd trcd trrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 page mode read (burst length=4, cas latency=3) (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read active read read read read precharge tac tac tac tac tac bank #0 idle bank #1 bank #2 bank #3 ap*
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 26 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 tras trp trcd twr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 q q q q q q d d d d d page mode read / write (burst length=8, cas latency=3) (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read write precharge tac bank #0 idle bank #1 bank #2 bank #3
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 27 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 autoprecharge read (burst length = 4, cas latency = 3) (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 trc trc tras trp tras trp trcd trcd tac tac active read ap* active read ap* raa rab raa caw rab cax aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 28 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 autoprecharge write (burst length = 4) (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 trc trc tras trp tras trp raa trcd trcd rab rac raa caw rab cax rac aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 active active write ap* active write ap* * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 29 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 autorefresh cycle (clk = 100 mhz) all banks prechage auto refresh auto refresh (arbitrary cycle) trc trp trc clk dq cke dqm a0-a9, a11 a10 we cas ras cs bs0,1
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 30 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 selfrefresh cycle (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs0,1 we cas ras cs tcks tsb tcks tcks all banks precharge self refresh entry arbitrary cycle trp self refresh cycle trc no operation cycle
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 31 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cs ras cas we bs0 bs1 a10 a0-a9, a11 dqm cke dq burst read and single write (burst lenght = 4, cas latency = 3) (clk = 100 mhz) trcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 q q q q d d d q q q q tac tac read read single write active bank #0 idle bank #1 bank #2 bank #3
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 32 - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 powerdown mode (clk = 100 mhz) raa caa raa cax raa raa ax0 ax1 ax2 ax3 tsb tcks tcks tcks tsb tcks active standby power down mode precharge standby power down mode active nop precharge nop active note: the powerdown mode is entered by asserting cke "low". all input/output buffers (except cke buffers) are turned off in the powerdown mode. when cke goes high, command input must be no operation at next clk rising edge. clk dq cke dqm a0-a9 a10 bs we cas ras cs
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 33 - autoprecharge timing ( read cycle ) q0 read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 act q0 q3 (2) cas latency=3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least tras(min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note ) trp trp trp trp trp trp trp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 trp
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 34 - autoprecharge timing ( read cycle ) read act ap read act ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 q0 q0 read ap act q1 read ap act q1 q1 q2 q2 q3 q3 q4 q5 q6 q7 ap act read (3) cas latency=4 when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least tras(min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note ) trp trp trp trp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 35 - autoprecharge timing ( write cycle ) d0 write act ap 0 11 10 9 8 7 6 5 4 3 2 1 d0 d0 d0 d0 ap act d1 ap act d1 d1 d2 d2 d3 d3 d4 d5 d6 d7 ap act ap act ap act d1 d0 ap act d1 d2 d3 ap act d0 d1 d2 d3 d4 d5 d6 d7 write write write write write write write d0 (1) cas latency=2 (2) cas latency=3 write act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least tras(min) . represents the write with auto precharge command. represents the start of internal precharging. represents the bank activate command. note ) trp twr trp twr trp twr trp twr trp twr trp twr trp twr trp twr ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 36 - autoprecharge timing ( write cycle ) write act ap 0 11 10 9 8 7 6 5 4 3 2 1 d0 d0 d0 d0 ap act d1 ap act d1 d1 d2 d2 d3 d3 d4 d5 d6 d7 ap act write write write (3) cas latency=4 write act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note ) trp twr trp twr trp twr trp twr dq dq dq dq ( a ) burst length = 1 ( b ) burst length = 2 ( c ) burst length = 4 ( d ) burst length = 8 command command command command
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 37 - note ) ? ?e the output data must be masked by dqm to avoid i/o conflict timing chart of read to write cycle read write 11 10 9 8 7 6 5 4 3 2 1 read read read read read write write d0 d1 d2 d3 write write write dq dq ( a ) command 0 dq dq dq dq dqm ( b ) command dqm ( b ) command dqm dqm ( a ) command dqm ( b ) command dqm d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 (1) cas latency=2 ( a ) command (3) cas latency=4 (2) cas latency=3 in the case of burst length=4
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 38 - timing chart of write-to-read cycle read write 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read read read read write write q0 q1 q2 q3 write write write q0 q1 q2 q3 d0 d1 q0 q1 q2 q3 d0 q0 q1 q2 q3 d0 d1 dq dq ( a ) command dq dq dq dq dqm ( b ) command dqm ( a ) command ( b ) command dqm dqm ( a ) command dqm ( b ) command dqm in the case of burst length=4 (1) cas latency=2 (2) cas latency=3 (3) cas latency=4 d0 d0 d1 q0 q1 q2 q3 d0
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 39 - timing chart of burst stop cycle ( burst stop command ) note ) represents the burst stop command bst dq dq read bst 0 11 10 9 8 7 6 5 4 3 2 1 d0 q0 q1 d1 q2 d2 q3 d3 dq dq q0 q1 q2 q3 q0 q1 q2 q3 write read read bst bst bst ( a ) cas latency =2 command ( b )cas latency = 3 command ( c )cas latency = 4 command command (3) read cycle (2) write cycle q4 q4 q4 d4
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 40 - timing chart of burst stop cycle ( precharge command ) in the case of burst lenght = 8 note ) represents the precharge command prcg read prcg 0 11 10 9 8 7 6 5 4 3 2 1 q0 q1 q2 q3 q0 q1 q2 q3 q0 q1 q2 q3 read read prcg q4 q4 prcg q4 write prcg d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 write write prcg d4 d4 prcg d4 dq ( a )cas latency =2 command ( b )cas latency = 3 command dq dq ( c )cas latency = 4 command dq dq ( b )cas latency = 3 command dq ( c )cas latency = 4 command dq ( a ) cas latency =2 command dqm dqm dqm dq (1) read cycle (2) write cycle dq twr twr twr
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 41 - cke/dqm input timing ( write cycle ) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 42 - cke/dqm input timing ( read cycle ) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 43 - asynchronous control input buffer turn on time ( power down mode exit time ) is specified by tcks(min) + tck(min) command nop clk cke command a ) t ck < tcks (min)+tck(min) t cks (min)+t ck (min) tck input buffer enable command clk cke command b) tck >= tcks(min) + tck (min) input buffer enable t ck t cks (min)+t ck (min) self refresh/power down mode exit timing note ) command nop all input buffer(include clk buffer) are turned off in the power down mode and self refresh mode represents the no-operation command represents one command
W986408BH 2m x 8 bit x 4 banks sdram revision 1.2 publication release date: april, 1999 - 44 - package dimension 54l tsop (ii)-400 mil seating plane e d a2 a1 a e b zd 1 27 54 28 h e y l c l1 zd 0.71 0.028 0.002 0.009 max. min. nom. a2 b a a1 0.24 1.00 0.05 0.40 1.20 0.15 symbol dimension (mm) max. min. nom. e 0.80 0.0315 0.016 l 0.40 0.50 0.60 0.020 0.024 0.396 e 10.06 10.16 10.26 0.400 0.404 0.871 d 22.22 22.12 22.62 0.875 0.905 0.039 0.016 0.047 0.006 dimension (inch) 0.10 0.004 0.32 l1 0.80 0.032 c 0.15 0.006 0.012 0.455 11.76 11.56 11.96 0.463 0.471 h y 0.10 0.004 controlling dimension : millimeters

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